Hardware Implementation of the SHA-3 Candidate Skein

Skein is a submission to the NIST SHA-3 hash function competition which has been optimized towards implementation in modern 64-bit processor architectures. This paper investigates the performance characteristics of a high-speed hardware implementation of Skein with a 0.18\,\textmu}m standard-cell library and on different modern FPGAs. The results allow a first comparison of the hardware performance figures of full Skein with other SHA-3 candidates

High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Grøstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein

In this paper we describe our high-speed hardware implementations of the 14 candidates of the second evalution round of the \mbox{SHA-3} hash function competition. We synthesized all implementations using a uniform tool chain, standard-cell library, target technology, and optimization heuristic. This work provides the fairest comparison of all second-round candidates to date

Compact Hardware Implementations of the SHA-3 Candidates ARIRANG, BLAKE, Grøstl, and Skein

The weakening of the widely used SHA-1 hash function has also cast doubts on the strength of the related algorithms of the SHA-2 family. The US NIST has therefore initiated the SHA-3 competition in order to select a modern hash function algorithm as a ``backup\u27\u27 for SHA-2. This algorithm should be efficiently implementable both in software and hardware under different constraints. In this paper, we present hardware implementations of the four SHA-3 candidates ARIRANG, BLAKE, Grøstl, and Skein with the primary constraint of minimizing chip area

A unique transcriptome: 1782 positions of RNA editing alter 1406 codon identities in mitochondrial mRNAs of the lycophyte Isoetes engelmannii

The analysis of the mitochondrial DNA of Isoetes engelmannii as a first representative of the lycophytes recently revealed very small introns and indications for extremely frequent RNA editing. To analyze functionality of intron splicing and the extent of RNA editing in I. engelmannii, we performed a comprehensive analysis of its mitochondrial transcriptome. All 30 groups I and II introns were found to be correctly removed, showing that intron size reduction does not impede splicing. We find that mRNA editing affects 1782 sites, which lead to a total of 1406 changes in codon meanings. This includes the removal of stop codons from 23 of the 25 mitochondrial protein encoding genes. Comprehensive sequence analysis of multiple cDNAs per locus allowed classification of partially edited sites as either inefficiently edited but relevant or as non-specifically edited at mostly low frequencies. Abundant RNA editing was also found to affect tRNAs in hitherto unseen frequency, taking place at 41 positions in tRNA-precursors, including the first identification of U-to-C exchanges in two tRNA species. We finally investigated the four group II introns of the nad7 gene and could identify 27 sites of editing, most of which improve base pairing for proper secondary structure formation

Complex chloroplast RNA metabolism: just debugging the genetic programme?

<p>Abstract</p> <p>Background</p> <p>The gene expression system of chloroplasts is far more complex than that of their cyanobacterial progenitor. This gain in complexity affects in particular RNA metabolism, specifically the transcription and maturation of RNA. Mature chloroplast RNA is generated by a plethora of nuclear-encoded proteins acquired or recruited during plant evolution, comprising additional RNA polymerases and sigma factors, and sequence-specific RNA maturation factors promoting RNA splicing, editing, end formation and translatability. Despite years of intensive research, we still lack a comprehensive explanation for this complexity.</p> <p>Results</p> <p>We inspected the available literature and genome databases for information on components of RNA metabolism in land plant chloroplasts. In particular, new inventions of chloroplast-specific mechanisms and the expansion of some gene/protein families detected in land plants lead us to suggest that the primary function of the additional nuclear-encoded components found in chloroplasts is the transgenomic suppression of point mutations, fixation of which occurred due to an enhanced genetic drift exhibited by chloroplast genomes. We further speculate that a fast evolution of transgenomic suppressors occurred after the water-to-land transition of plants.</p> <p>Conclusion</p> <p>Our inspections indicate that several chloroplast-specific mechanisms evolved in land plants to remedy point mutations that occurred after the water-to-land transition. Thus, the complexity of chloroplast gene expression evolved to guarantee the functionality of chloroplast genetic information and may not, with some exceptions, be involved in regulatory functions.</p

Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography

The Advanced Encryption Standard (AES) specifies an algorithm for a symmetric-key cryptosystem that has already found wide adoption in security applications. A substantial part of the AES algorithm are the MixColumns and InvMixColumns operations, which involve multiplications in the binary extension field GF(2 8). Recently proposed instruction set extensions for elliptic curve cryptography (ECC) include custom instructions for the multiplication of binary polynomials. In the present paper we analyze how well these custom instructions are suited to accelerate a software implementation of the AES. We used the SPARC V8-compatible LEON-2 processor with ECC extensions for verification and to obtain realistic timing results. Taking the fastest implementation for 32-bit processors as reference, we were able to achieve speedups of up to 25 % for encryption and nearly 20 % for decryption

Instruction Set Extensions for Ef£cient AES Implementation on 32-bit Processors

Abstract. Secure communication over public networks like the Internet requires the use of cryptographic algorithms as basic building blocks. Most cryptographic workloads pose a considerable burden on devices like PDAs, cell phones, and sensor nodes, which are limited in processing power, memory and energy. In this paper we present an approach to increase the ef£ciency of 32-bit processors for handling symmetric cryptographic algorithms with the help of instruction set extensions. We propose a number of custom instructions to support the Advanced Encryption Standard (AES). Using the SPARC V8-compatible Leon2 embedded processor, we evaluate the effects of the extensions on performance and code size of AES, as well as on silicon area. With a moderate increase in silicon area, AES performance can be improved by a factor of nearly 10, while code size is reduced signi£cantly and implementation ¤exibility is retained. We also show that our approach is very bene£cial for implementation in superscalar processors and that it can compete with the performance of previously proposed cryptographic processors and instruction set extensions

Power Analysis Resistant AES Implementation with Instruction Set Extensions

In recent years, different instruction set extensions for cryptography have been proposed for integration into general-purpose RISC processors. Both public-key and secret-key algorithms can profit tremendously from a small set of custom instructions specifically designed to accelerate performance-critical code sections. While the impact of instruction set extensions on performance and silicon area has been widely investigated in the recent past, the resulting security aspects (i.e. resistivity to side-channel attacks) of this particular design approach remain an open research topic. In this paper we discuss and analyze different techniques for increasing the side-channel resistance of AES software implementations using instruction set extensions. Furthermore, we propose a combination of hardware and software-related countermeasures and investigate the resulting effects on performance, cost, and security. Our experimental results show that a moderate degree of protection can be achieved with a simple software countermeasure. Hardware countermeasures, such as the implementation of security-critical functional units using a DPA-resistant logic style, lead to much higher resistance against side-channel attacks at the cost of a moderate increase in silicon area and power consumption